Cascaded Feedforward Sigma-delta Modulator for Wide Bandwidth Applications

Jen-Shiun Chiang; Teng-Hung Chang; Pou-Chu Chou

doi:10.6180/jase.2001.4.3.02

Cascaded Feedforward Sigma-delta Modulator for Wide Bandwidth Applications

Jen-Shiun Chiang This email address is being protected from spambots. You need JavaScript enabled to view it.¹, Teng-Hung Chang¹ and Pou-Chu Chou¹

¹

Received: June 22, 2001
Accepted: July 27, 2001
Publication Date: September 1, 2001

Download Citation: ||https://doi.org/10.6180/jase.2001.4.3.02

ABSTRACT

A new sigma-delta modulator architecture for wide bandwidth application called cascaded feedforward sigma-delta modulator is proposed in this paper. This sigma-delta modulator is similar to the conventional feedforward summation sigma-delta modulator. The conventional feedforward summation sigma-delta modulator uses multi-bit feedback and therefore a multi-bit digital-to-analog converter (DAC) is needed. Due to the nonlinearity of the multi-bit DAC, it is difficult to be implemented. On the other hand the proposed approach uses 1.5-bit feedback, and thus the implementation of the analog part is much easier than the conventional one. Since the 1.5-bit feedback will cause coarse quantization errors, error cancellation must be done in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the signal to noise plus distortion ratio (SNDR) of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide bandwidth application.

Keywords: Wide-bandwidth, Cascaded Sigma-delta Modulator, Feedforward, xDSL, Dual-quantizer

REFERENCES

[1] Candy, J. C. and Temes, G. C., Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, New York (1992).
[2] Chao, K. C., Nadeen, S., Lee, W. L., and Sodini, C. G., “A higher order topology for interpolative modulators for oversampling A/D converter,” IEEE Trans. Circuits and Syst., Vol. 37, pp. 309-318 (1990).
[3] Cini, D., Samori, C. and Lacaita, A. L., “Double-index averaging: a novel technique for dynamic element matching in SigmaDelta A/D converters,” IEEE Trans. Circuits and Syst. II, Vol. 46, pp. 353-358 (1999).
[4] Ferguson, P. F., Ganesan, Jr. A. and Adams, R. W., “One bit higher order sigma-delta A/D converters,” IEEE Proc. of ISCAS, Vol. 2, pp. 890-893 (1990).
[5] Kenney, J. G. and Carley, L. R., “Design of multi-bit noise-shaping data converters,” Analog Int. Circuits Signal Proc. Journal (Kluwer), Vol. 3, pp. 259-272 (1993).
[6] Kiss, P., Silva, J., Wiesbauer, A., Sun, T., Moon, U. -K., Stonick, J. T. and Temes, G. C., “Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection,” IEEE Trans. Circuits and Syst. II, Vol. 47, pp. 629-638 (2000).
[7] Kuo, T. H., Chen, K. D. and Chen, J. R., “Automatic coefficients design for high-order sigma-delta modulator,” IEEE Trans. Circuit and Syst. II, Vol. 46, pp. 6-15 (1999).
[8] Norsworthy, S. R., Schreier, R. and Temes, G. C., Delta-Sigma Data Converters: Theory Design, and Simulation, IEEE Press, New York (1997).
[9] Nys, O. and Henderson, R. K., “A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging,” IEEE Journal of Solid-State Circuits, Vol. 32, pp. 933-942 (1997).
[10] Rabii, S. and Wooley, B. A., The Design of Low-Voltage, Low-Power Sigma-delta Modulators, Kluwer Academic Publishers, Boston/Dordrecht/London (1999).
[11] Risbo, L., “Stability prediction for high-order Σ-∆ modulators based on quasi linear modeling,” IEEE Proc. of ISCAS, pp. 361-364 (1994).
[12] Schreier, R., “An empirical study of high-order single-bit delta-sigma modulators,” IEEE Trans. Circuits and Syst. II, Vol. 40, pp. 461-466 (1993).
[13] Wiesbauer, A. and Temes, G. C., “On-line digital compensation of analog circuit imperfections for cascaded Σ∆ modulator,” IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, pp. 92-97 (1996).