A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits

Jiann-Chyi  Rau; Po-Han Wu; Ying-Fu  Ho

doi:10.6180/jase.2008.11.2.09

A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits

Jiann-Chyi Rau This email address is being protected from spambots. You need JavaScript enabled to view it.¹, Po-Han Wu¹ and Ying-Fu Ho¹

¹Department of Electrical Engineering, Tamkang University, Tamsui, Taiwan 251, R.O.C

Received: April 11, 2006
Accepted: August 13, 2007
Publication Date: June 1, 2008

Download Citation: ||https://doi.org/10.6180/jase.2008.11.2.09

ABSTRACT

During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns can’t detect fault (called useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In fact, a random test set includes many useless patterns. Therefore we present a technology, including both reseeding and bit modifying (a.k.a. pattern mapping) to remove useless patterns or change them to useful patterns. When patterns changed, we pick out number of different fewer bits, leading to very short test length. Then we use an additional bit counter to improve test length and achieve high fault coverage. The technique we present is applicable for single-stuck-at faults. Experimental results indicate that complete fault coverage-100% can be obtained with less test time.

Keywords: BIST, LFSR, Pseudo-Random Testing, Reseeding

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