Journal of Applied Science and Engineering

Published by Tamkang University Press

1.30

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2.10

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Ganjikunta Ganesh Kumar1This email address is being protected from spambots. You need JavaScript enabled to view it., Sibghatullah Inyatullah Khan1, G Prasad Acharya1, and Shravan Kumar S M2

1Department of Electronics and Communication Engineering, Sreenidhi Institute of Science and Technology, Hyderabad, India

2Department of Civil Engineering, Sreenidhi Institute of Science and Technology, Hyderabad, India


 

 

Received: January 6, 2024
Accepted: December 17, 2024
Publication Date: January 23, 2025

 Copyright The Author(s). This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are cited.


Download Citation: ||https://doi.org/10.6180/jase.202510_28(10).0008  


This paper introduces an innovative solution for increasing precision of fixed-width radix-4 Booth multipliers through variable error compensation functions that leverage Approximation of Carry Function (ACF). Error compensation mechanisms typically comprise two carries-ideal and base carry functions–strategically chosen to minimize mean error. We present three distinct methods-ACF-1, ACF-2, and ACF-3—each employing fixed base values with varying column information (w) and bit lengths (N). Comparative analyses against recent studies demonstrate that our proposed fixed-width Booth multiplier using ACF-1 stands out in terms of accuracy and efficiency tradeoffs.


Keywords: Error-compensation function; Fixed-width multiplier; Ideal and base carry functions


  1. [1] C. R. Baugh and B. A. Wooley, (1973) “A two’s com plement parallel array multiplication algorithm" IEEE Transactions on computers 100(12): 1045–1047. DOI: 10.1109/T-C.1973.223648.
  2. [2] J.-H.TuandL.-D.Van,(2009)“Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers" IEEE transactions on computers 58(10): 1346–1355. DOI: 10.1109/TC.2009.89.
  3. [3] A. Badawi, A. Alqarni, A. Aljuffri, M. S. BenSaleh, A. M. Obeid, and S. M. Qasim. “FPGA realization and performance evaluation of fixed-width modi f iedBaugh-Wooleymultiplier”. In: 2015 Third Interna tional Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE). IEEE. 2015, 155–158. DOI: 10.1109/TAEECE.2015.7113618.
  4. [4] R. Keote and P. Karule, (2018) “Performance Analysis of Fixed Width Multiplier using Baugh Wooley Algo rithm" International Organization of Scientific Re search Journal of Very Large-Scale Integration and Signal Processing 8(3): 31–38. DOI: 10.9790/4200-0803013138.
  5. [5] A. D. Booth, (1951) “A signed binary multiplication technique" The Quarterly Journal of Mechanics and Applied Mathematics 4(2): 236–240. DOI: 10.1093/qjmam/4.2.236.
  6. [6] L.-D. Van, S.-S. Wang, and W.-S. Feng, (2000) “Design of the lower error fixed-width multiplier and its applica tion" IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47(10): 1112–1118. DOI: 10.1109/82.877155.
  7. [7] S.-J. Jou, M.-H. Tsai, and Y.-L. Tsao, (2003) “Low-error reduced-width Booth multipliers for DSP applications" IEEETransactionsonCircuitsandSystemsI:Funda mental Theory and Applications 50(11): 1470–1474. DOI: 10.1109/TCSI.2003.817779.
  8. [8] K.-J. Cho, K.-C. Lee, J.-G. Chung, and K. K. Parhi, (2004) “Design of low-error fixed-width modified booth multiplier" IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12(5): 522–531. DOI: 10.1109/TVLSI.2004.825853.
  9. [9] J.-P. Wang,S.-R. Kuang, andS.-C. Liang, (2009) “High accuracy fixed-width modified booth multipliers for lossy applications" IEEE transactions on very large scale integration (VLSI) systems 19(1): 52–60. DOI: 10.1109/TVLSI.2009.2032289.
  10. [10] C.-Y. Li, Y.-H. Chen, T.-Y. Chang, and J.-N. Chen, (2011) “A probabilistic estimation bias circuit for fixed width Booth multiplier and its DCT applications" IEEE Transactions on Circuits and Systems II: Express Briefs 58(4): 215–219. DOI: 10.1109/TCSII.2011.2111610.
  11. [11] Y.-H.Chen,(2014)“Anaccuracy-adjustmentfixed-width booth multiplier based on multilevel conditional probabil ity" IEEE transactions on very large scale integra tion (VLSI) systems 23(1): 203–207. DOI: 10.1109/TVLSI.2014.2302447.
  12. [12] W.-Q. He, Y.-H. Chen, and S.-J. Jou, (2015) “High accuracy fixed-width booth multipliers based on proba bility and simulation" IEEE Transactions on Circuits andSystemsI: Regular Papers 62(8): 2052–2061. DOI: 10.1109/TCSI.2015.2440731.
  13. [13] G. G. Kumar and S. K. Sahoo. “Power-delay prod uct minimization in high-performance fixed-width multiplier”. In: TENCON 2015-2015 IEEE Region 10 Conference. IEEE. 2015, 1–4. DOI: 10.1109/TENCON.2015.7372864.
  14. [14] Z.ZhangandY.He,(2017)“Alow-errorenergy-efficient f ixed-width booth multiplier with sign-digit-based condi tional probability estimation" IEEE Transactions on Circuits and Systems II: Express Briefs 65(2): 236 240. DOI: 10.1109/TCSII.2017.2709801.
  15. [15] Y. He, X. Yi, Z. Zhang, B. Ma, and Q. Li, (2020) “A probabilistic prediction-based fixed-width booth multiplier for approximate computing" IEEE Transactions on Cir cuits and Systems I: Regular Papers 67(12): 4794 4803. DOI: 10.1109/TCSI.2020.3001654.
  16. [16] Z. Aizaz and K. Khare, (2021) “Area and power effi cient truncated booth multipliers using approximate carry based error compensation" IEEE Transactions on Cir cuits and Systems II: Express Briefs 69(2): 579–583. DOI: 10.1109/TCSII.2021.3094910.
  17. [17] R.Marimuthu,Y.E.Rezinold,andP.S.Mallick,(2016) “Design and analysis of multiplier using approximate 15-4 compressor" IEEE Access 5: 1027–1036. DOI: 10.1109/ACCESS.2016.2636128.
  18. [18] M. H. Haider and S.-B. Ko, (2023) “Booth encoding based energy efficient multipliers for deep learning sys tems" IEEE Transactions on Circuits and Systems II: Express Briefs 70(6): 2241–2245. DOI: 10.1109/TCSII.2022.3233923.
  19. [19] R. Marimuthu, D. Bansal, S. Balamurugan, and P. Mallick, (2013) “Design of 8-4 and 9-4 compressors forhigh speed multiplication" American Journal of Ap plied Sciences 10(8): 893. DOI: 10.3844/ajassp.2013.893.900.
  20. [20] R. Marimuthu and P. Mallick, (2017) “Design of Effi cient Signed Multiplier Using Compressors for FFT Ar chitecture." Journal of Engineering Science & Tech nology Review 10(2): DOI: 10.25103/jestr.102.13.
  21. [21] E. Zacharelos, I. Nunziata, G. Saggese, A. G. Strollo, and E. Napoli, (2022) “Approximate recursive multipli ers using low power building blocks" IEEE Transactions on Emerging Topics in Computing 10(3): 1315–1330. DOI: 10.1109/TETC.2022.3186240.
  22. [22] R. Marimuthu, S. Balamurugan, and P. S. Mallick, (2018) “Design of 5-3 multicolumn compressor for high performance multiplier" International Journal of Com puter AidedEngineeringandTechnology10(5):568 575. DOI: 10.1504/IJCAET.2018.094334.
  23. [23] W.Liu, T. Cao, P. Yin, Y. Zhu, C. Wang, E. E. Swartz lander, and F. Lombardi, (2018) “Design and analysis of approximate redundant binary multipliers" IEEE Trans actions on computers 68(6): 804–819. DOI: 10.1109/TC.2018.2890222.


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