Journal of Applied Science and Engineering

Published by Tamkang University Press

1.30

Impact Factor

2.10

CiteScore

Fangfei Han, Zheng Lu, Luan Fu, Lulu DuThis email address is being protected from spambots. You need JavaScript enabled to view it., and Xiaohui ShiThis email address is being protected from spambots. You need JavaScript enabled to view it.

School of Physics and Electronic Engineering, Linyi University, Linyi, 276000, China


 

Received: October 30, 2024
Accepted: December 17, 2024
Publication Date: January 24, 2025

 Copyright The Author(s). This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are cited.


Download Citation: ||https://doi.org/10.6180/jase.202510_28(10).0011  


Asputtered silicon dioxide dielectric is prepared for fabrication of indium gallium zinc oxide (IGZO) thin-film transistors (TFTs). We analyzed the dependence of device characteristics on gate voltage range. Clockwise hysteresis occurs at a low gate voltage ( Vgs ≤ 3 V) due to oxide traps near the SiO2/IGZO interface. At higher gate voltage Vgs = 5 V a second, hysteresis collapse appears, which can be attributed to the coexistence of electron trapping and ion migration with a compatible and the opposite contributions to the hysteresis. Due to the dominant ion migration, hysteresis inversion (clockwise to anti-clockwise) appears at Vgs = 7 V. At Vgs = 10V,devices performance degrades significantly, which may be ascribed to the electrochemical reaction. Further, a bias stress measurement indicates that the devices work effectively under a wide range Vgs of 1 ∼ 7 V.

 


Keywords: Indium Gallium Zinc Oxide (IGZO); Thin-Film Transistors (TFTs); Hysteresis; Sputtered SiO2


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2.1
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69th percentile
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